A flip-chip ball grid array (FCBGA) semiconductor package incorporates a flip-chip structure and a ball grid array, wherein an active surface of a chip is electrically connected to a first surface of a substrate via a plurality of solder bumps, and a plurality of solder balls are mounted on a second surface of the substrate opposite to the first surface and serve as input/output (I/O) connections. This type of package structure has an advantage of great decrease in size, without using conventional bonding wires. Therefore, impedance or resistance of signal transmission can be reduced while electrical performance would be improved, making the FCBGA package become the mainstream of packaging technology for chips and electronic elements of the next generation.
The FCBGA package is suitably incorporated with multiple chips for high integration and desirable operating performance. Since a multi-chip package generates more heat than a single-chip package, heat dissipation is a crucial factor affecting the performance of the multi-chip package. In a conventional FCBGA package, a heat sink is directly adhered to a non-active surface of a chip mounted in the package to dissipate heat from the chip, rather than dissipating heat via an encapsulating material having poor thermal conductivity, such that the heat dissipating efficiency of this FCBGA package is relatively better than other types of packages.
The above FCBGA package is illustrated in FIG. 17, wherein a supporting part 60b of a heat sink 60 is adhered onto a substrate 62 via an adhesion 61. A flat part 60a of the heat sink 60 is adhered onto a non-active surface 64a of a chip 64 via a thermal paste 63. The heat generated by operation of the chip 64 is dissipated through the exposed flat part 60a of the heat sink 60. U.S. Pat. Nos. 5,311,402, 5,909,474, 5,909,057 and 5,637,920 disclose similar structures to that shown in FIG. 17. However, the heat sink may be fixed in position by different mechanisms; for example, the heat sink can be screwed or fastened by a bolt or other fasteners to the substrate so as to increase bonding between the heat sink and the substrate.
The configuration of the heat sink having the supporting part and the flat part remains substantially unchanged during the evolution and development of the packaging technology. This is because, in the FCBGA package, the heat sink not only defines a space by the flat part and the supporting part in which the chip is received, but also serves a lid to cover the substrate. Therefore, a cross-sectional view of the heat sink appears to be shaped as an upward recess shown in FIG. 17. And the space defined by the heat sink is increased in size according to the number of chips being accommodated therein, making the profile of the package correspondingly increased.
As a result, the configuration of the above upwardly-recessed shaped heat sink sets a limitation in improving the FCBGA package structure and is not desirable for realization of packages with high heat dissipating efficiency, low fabrication cost and small size. Such a conventional heat sink is manufactured by the forging technique to form the flat part and the supporting part. As shown in FIG. 18A and FIG. 18B, a square heat sink 60, for example, is formed by placing a copper or aluminum sheet in a mold at a high temperature and then punching or pressing the sheet at a forging temperature to form a space or recess 65. The chip 64 is accommodated in the space 65 when the heat sink 60 is attached onto the substrate 62. This method is limited by operation of the forging machine and forging hammer and its equipment cost. This is not favorable to the throughput and would cause an increase in the production cost when the size of the heat sink is changed.
Furthermore, the forging method has a problem of limited molding precision. The aspect ratio (t/T) of the heat sink as shown in FIG. 18A and FIG. 18B has a certain upper limit, such that the total thickness T of the heat sink 60 cannot be further close to the height t of the accommodating space 65. Currently, the aspect ratio (t/T) is at most about 0.5. That is, the total thickness T of the heat sink 60 is determined according to the height t of the space 65 to be formed. If the height t of the accommodating space 65 is 1 mm, then the sheet used to form the heat sink 60 needs to be at least 2 mm thick for forging. Therefore, when the thickness of the chip 64 mounted or the number of chips stacked on the substrate 62 is increased, the height t of the space 65 has to be correspondingly increased and the thickness T of the heat sink 60 has to be proportionally increased. As a result, the overall size of the package is difficult to be reduced, which is not favorable to the current trend of size miniaturization. Further, the thickness of the heat sink 60 is increased with the thickness or number of the chip 64, which is detrimental to dissipation of heat from the chip 64.
Referring to FIG. 19 showing a dual-chip package, as compared to the above single-chip package of FIG. 17, the increase in thickness of this dual-chip package includes the thickness of the extra chip 66 and the increase in thickness of the heat sink 60 formed by forging whose total thickness T is raised according to the increased height t of the accommodating space 65 for accommodating the two chips 64, 66. As a result, not only the overall size of the package is increased, but also the fabrication or material cost for the heat sink is increased while the heat efficiency would be reduced in the use of such a thicker heat sink.
The heat sink formed by forging is limited to the type and size of the forging hammer, thereby not allowing desirable flexibility in size and shape of the heat sink for increasing its heat dissipating area. Referring to FIG. 20, additional heat dissipating fins 67 are mounted on the flat part 60a of the heat sink 60 to increase the external contact area. Due to design limitations, the fins 67 are located only right above the flat part 60a, which results in significant increase in the total thickness of the package. Referring to FIG. 21, a passive component 68 is additionally mounted on the substrate 62 to increase the electrical performance of the package, and the accommodating space 65 of the heat sink 60 needs to be enlarged for receiving the passive component 68. However, with the limitation of the size of the forging hammer, the size and shape of the heat sink 60 cannot be flexibly modified according to the layout on the substrate 62, such that fabrication of a batch of new products is required, thereby setting a substantial limitation to wire routing.
In the conventional process, the punching force of the forging hammer at a high temperature forms the accommodating space of the heat sink. When the process is completed, a residual stress is left at a periphery of the accommodating space of the heat sink due to stress concentration, which damages the crystal cells of the copper or aluminum. Therefore, after the package provided with the heat sink has undergone reliability tests or a long-term use, the boundary between the flat part 60a and the supporting part 60b of the heat ink 60 may suffer a crack 69 due to the residual stress, as shown in FIG. 22. The crack 69 may expand and damage the structure of the heat sink 60.
Furthermore, the conventional heat sink also has the following disadvantages. The flat part and the supporting part of the heat sink are integrally formed. The heat sink is mounted on the substrate by attaching the supporting part to the substrate, and the flat part of the heat sink is in contact with the chip. There is a great difference between the respective coefficients of thermal expansion (CTE) of the heat sink and the chip. When the package is subjected to high temperature processing, the flat part of the heat sink is deformed more seriously than the chip. Since the periphery of the flat part is sustained by the supporting part, the thermal strain is difficult to release, and the deformation of the heat sink as shown in FIG. 23 is generated. As a result, delamination 70 is generated between the flat part 60a and the chip 64 or between the flat part 60a and the thermal paste 63, thereby reducing the heat dissipating efficiency of the package. When the package with the deformed heat sink 60 is subject to an external shock, the supporting part 60b of the heat sink 60 may be delaminated from the substrate 62, thereby making the heat sink 60 uncoupled from the substrate 62.
The heat sink is used for heat dissipation of the FCBGA package. However, as the electronic device has been developed with increasingly high integration and heat dissipation and decreasingly low cost and small size, the limitations of size and production process of the heat sink are to be overcome for the next generation of packages. Slight modification to the structure of the heat sink formed by the current forging process cannot overcome all the problems in the art.
Therefore, there is a need of a semiconductor package having a heat dissipating structure formed without the limitation of the aspect ratio, such that the heat dissipating performance can be increased, and the beat sink can be flexibly sized, so as to solve the foregoing prior-art problems.